Well IIRC, the amount of execution units presented architecturally are not actually reflected to what is available internally. This was done to allow them to increase the number units under the hood without breaking backward compatibility (or is it forward compatibility in this case). At which point, you still are going to need scheduling hardware and all that jazz.
That said, to my limited understanding, all processors are internally VLIW, it's just hidden behind a decoder & scheduler that exposes are more limited ISA so that they don't have to make the trade-off Itanium did.
That said, I really wonder if it's an issue of compiler was too complicated to bootstrap one good enough to get the ecosystem going, or if it was a truly brainded evolutionary fork. Anyone seem any good hand optimised benchmarks to see the potential of the paradigm?
Btw, it looks like someone started adding IA64 support to QEMU: https://github.com/amarioguy/qemu-itanium
It's good to have that available. Students can examine actual software for hardware that'll soon be recycled.
Maybe GPU usage as well. I know very little about what the ISA of GPUs looks like though.
They moved to SIMD. Not sure what they're doing in their latest as I haven't been paying attention lately.
[1]: https://www.anandtech.com/show/4455/amds-graphics-core-next-...
Note that I vaguely remember having read somewhere that EPIC isn't "true" VLIW (whatever that means), unlike what you can find in some camera SoCs (e.g. Fujitsu FR-V).