>> Many modern CPUs use different voltage levels for certain components, and everything works fine.

But none of them use more than 2 states. If you've got a circuit at 0.9V or one at 2.5V they both have a single threshold (determined by device physics) that determines the binary 1 or 0 state and voltages tend toward 0 or that upper supply voltage. There is no analog or level-based behavior. A transistor is either on or off - anything in the middle has resistance and leads to extra power dissipation.

Isn't high speed signalling full of examples for multi level (as in, more-than-two level) signals? PCI-E's gen 6 and the various wireless standards come to mind.

At least as things stand now, these signals are only used when absolutely necessary, and no real work is done on them directly. Transmitting many bits in parallel was the original way of doing this, and would still be preferred if feasible, but timing issues arise at modern speeds over long distances (10s of cm). So the signals on one board, which are still binary and parallel, are multiplexed into a multi-level serial signal before transmission, transmitted over the serial data lines, and then received and demultiplexed on the other board from multi-level serial back into binary parallel signals. All computation (logic and arithmetic) operates on the binary signals, not the multi-level signals.

In limited, specialized domains where big chunky (comparatively) transceivers let you abuse "actually analog" naturę of the medium for higher speeds.

Not for internal logic.

> various wireless standards

Electromagnetic waves do not interact with one another, so it is difficult to build a transistor with it. There's some research into optical transistors but doesn't seem to work well yet.

As mentioned by another comment, NAND has multiple voltage levels.

   - Single-level cell (SLC) flash: One bit per cell, two possible voltage states
   - Multi-level cell (MLC) flash: Two bits per cell, four possible voltage states
   - Triple-level cell (TLC) flash: Three bits per cell, eight possible voltage states
   - Quad-level cell (QLC) flash: Four bits per cell, 16 possible voltage states

NAND flash is so-named because of its physical resemblance to a NAND gate, but I don't think it actually functions as a NAND gate.

Put another way, is it possible to feed two 16-level signals (X and Y) into a QLC and get a 16-level result back out of it (Z), where Z = X NAND Y, and if so, is it significantly faster, smaller, or less power-hungry than 4 conventional NAND gates running in parallel? I don't think so.

As it stands, NAND flash cells are only used for storage, and that's because of their high information density, not any computational benefits. Once the signals leave the SSD, they've already been converted to binary.

> is it significantly faster, smaller, or less power-hungry than 4 conventional NAND gates running in parallel?

It's not implemented any one of these several manners just for the hell of it. Everything has tradeoffs (which vary with each manufacturing node, architecture and timing in the market price landscape). The engineering and product management teams are not throwing darts. Most of the time anyway.

Saying that it's still binary because you feed binary into the chip and get binary back is moving the goal post (imo). A multilevel subsystem in a larger one is still multilevel, an analog one is still analog, an optical one is still optical (see switching fabric recently.)

So anyway, the russian systems did explore what could be done. The flash storage does answer some favorable tradeoff. And so have countless university projects. Including analog neural net attempts.

The second half of that question is not relevant if the answer to the first half of the question is "no" (it wasn't rhetorical). QLC "NAND" is not a logic gate, it is a storage mechanism. It does not compute anything.

Modern magnetic hard drives use all sorts of analog tricks to increase information density but few would seriously argue that this constitutes a fundamentally different kind of computing.

Yes, QLC (etc.) is an innovation for data storage (with tradeoffs). No, it is not a non-binary computer hiding in plain sight.

Fair enough. Common examples in storage and transmission. Not so common in computing for now. The closest obvious computing example, to my mind, is analog neural net blocks meant to be integrated in digital (binary) systems. Not ternary, old school (hah!) analog.

NAND flash has multiple different charge levels. This doesn't necessarily require different voltage levels.

Another comment suggest that NAND chips use 8 different voltages / states to encode 3 bits just in voltage states.

For data storage, not computation.

I don't really understand that distinction?

What makes data storage inherently different on the gate level?

Solving that issue has some characteristics that makes multistate voltage a good choice, but sure, that is the circumstances under whish you would use it.

Yes, and there is considerable electronics required in the readout logic to make sure that they are identified correctly, including error correction. That's not practicable for anything but storage or maybe off-chip/high-speed connections.

Actually, I have to correct myself. Charge levels, not voltage levels, and you do not necessarily need to have multiple voltage levels on the driving side to set these charge levels, you can do it by varying the write time.

Not agreeing with the parent post, but the different domains in modern electronics only work because they're (nominally) isolated except for level crossing circuits.

Your post is Dunning-Kruger at work.