Checking sketchier places Win-Source has the CLG400 package for $22.20 and even the cheapest aliexpress seller wants $4.84 for something marked as a 7Z010 that may or may not be legit.
Also "fight the chip" is pretty much the definition of what I did last time I did a zynq project. Just give me a plain FPGA and MCU with no wizards or GUIs or automatic code generation.
I've ordered trays (and they send the OEM tray) - unique barcodes, legit.
> Just give me a plain FPGA and MCU with no wizards or GUIs or automatic code generation.
You can pretty much cut out all of their tools and get a pure Yocto/Vivado TCL build for the bitstream for the 7 series Zynqs. Very low touch.
Their IO planner (in the Vivado IP integrator) is somewhat necessary for complex peripheral scenarios and is one of the few things I ever use Xilinx GUI applications for anymore.
On the chance they're half reasonable, thanks for the link.
I've previously struggled to roll the dice for higher end parts as the cost difference isn't as extreme and had some obvious reballed parts a few years ago. If they're OK then their $20 XC7K325T will be at the top of my list...
In the way that that Aliexpress vendor lists the 7010 parts at 1/10th the price of LCSC, some of their $20-60 listings are also shockingly cheap in comparison.
Thanks for your write-ups btw, been following glScope development for a while.
Nowadays, I only often wish I had their ARMv8 chips instead of the old ARMv7 32bit architecture because that’s just showing its age, but that’s par for the course of using ARMv7, and doesn’t affect the PL side (much, except for interfacing sometimes).
I've always wanted to do an FPGA project but haven't looked seriously into where to start. Can the Zynq 7010 handle something like data transfer from a 4K image sensor to a USB 3 transceiver?
> PIO has extraordinarily sloppy timing
Do you have any data on this? I was under the impression the PIO has fairly precise timing if you set up your clocks right, but maybe I've been misled here.
The Zynq 7010 is less-than-ideal for this because you'd have to use some kind of USB3 interface PHY - which would increase cost and be pretty limited functionality-wise.
If you use an FPGA with transceivers (some 7 series Artix chips - https://www.lcsc.com/product-detail/Programmable-Logic-Devic..., most 7 series Virtex/Kintex chips, all US/US+ chips), you can implement USB3 without an external PHY: https://github.com/enjoy-digital/usb3_pipe
The Z7010 probably has the area to do this type of translation but not the transceivers. There are other chips in the 7 series Zynq family with capable transceivers, but they are much more expensive ($15-$35 from CN).
> I was under the impression the PIO has fairly precise timing if you set up your clocks right, but maybe I've been misled here.
No measured data, but when I was once implementing JTAG and SPI at 50MHz+ with an extremely overclocked chip, the edges were very inconsistent in relation to each other and in pulse width - 5-15ns (estimating from memory, they were sloppy.)
PIO is very precise within its specified capabilities, this range is just very low compared to cheap FPGAs.
> PIO is very precise within its specified capabilities, this range is just very low compared to cheap FPGAs.
Good to know, I don't plan on pushing RP2040s to their limit any time soon. They're still excellent for lower speed projects.
PIO has extraordinarily sloppy timing (skew in all categories) compared to the cheapest and smallest FPGAs.