Re:Why do CPUs have multiple cache levels? (2016)
by bobmcnamara on Friday May 17, 2024 @07:43AM
(#40388827)
eDRAM L4 has been a thing in some Intel designs, but other than that, you're absolutely right
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Re:Why do CPUs have multiple cache levels? (2016)
by Symmetry on Friday May 17, 2024 @08:39AM
(#40389236)
Also a few IBM designs. An interesting thing is that IBM claimed that eDRAM was faster than SRAM for their particular design because at the scale they were using it the reduced size of the array increased speed more than eDRAM's access time decreased it.