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Re:ESP32-S3 has a few SIMD instructions by bobmcnamara on Sunday May 05, 2024 @03:04PM (#40267303)
IIRC, they have 128bit alignment requirements, so tricky to autovectorize.
Re:ESP32-S3 has a few SIMD instructions by bitbank on Monday May 06, 2024 @07:40AM (#40273463)
True - load and store mask off the bottom 4 bits of the address. They try to help the situation by including an instruction which can shift a pair of 128-bit registers by bytes.
Re:ESP32-S3 has a few SIMD instructions by bobmcnamara on Thursday May 09, 2024 @08:59PM (#40314522)
That sounds really familiar. Maybe Altivec did that? I remember it did something like that but I wish that it would just fault.