News for hackers. Stuff that matters.

A comment on More on x86 – The Chip Letter. Parent comment

Re:More on x86 – The Chip Letter by sudosysgen on Thursday April 25, 2024 @02:35PM (#40161330)
The L1 latency constraint is a size constraint - if you increase the L1 size, you simply cannot avoid increasing L1 latency.
[ Parent | on HN ]
Re:More on x86 – The Chip Letter by gpderetta on Thursday April 25, 2024 @04:29PM (#40162603)
That's what I meant: for performance considerations, L1 latency must be limited to single digit cycles on a general purpose CPU, hence L1 size is capped.
[ Parent | on HN ]