More on x86 – The Chip Letter

Re:More on x86 – The Chip Letter by gpderetta on Thursday April 25, 2024 @10:21AM (#40157946)

Re 4, cpus already have huge caches. L1s sizes are limited by latency constraints, not area. CPUs are power limited, not area limited (see dark silicon) and designers find creative ways to use otherwise unused space (hence the giant SIMD ALUs).

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Re:More on x86 – The Chip Letter by sudosysgen on Thursday April 25, 2024 @02:35PM (#40161330)

The L1 latency constraint is a size constraint - if you increase the L1 size, you simply cannot avoid increasing L1 latency.

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Re:More on x86 – The Chip Letter by gpderetta on Thursday April 25, 2024 @04:29PM (#40162603)

That's what I meant: for performance considerations, L1 latency must be limited to single digit cycles on a general purpose CPU, hence L1 size is capped.

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