Re:AMD announces the Spartan UltraScale+ FPGA family
by hobo_mark on Monday March 11, 2024 @08:18AM
(#39667218)
An FPGA is a blank slate, more so than a CPU is, the programming interface is whatever the user wants to implement (including ring buffers and DMA or whatever).
Re:AMD announces the Spartan UltraScale+ FPGA family
by delfinom on Monday March 11, 2024 @08:29AM
(#39667335)
In FPGAs you are literally programming the enablement of individual logic gates. That's it.
There is no DMA or command ring, you have to implement it yourself.
The FPGA bit code itself is extremely propertiary to each vendor as the nature of controlling all the logic sauces is all secret sauce. So you have to use the vendors tooling.
Re:AMD announces the Spartan UltraScale+ FPGA family
by sylware on Monday March 11, 2024 @09:52AM
(#39668236)
If we have to go thru a closed source or brain damaged hardware programming interface, this is a loss for us.
Re:AMD announces the Spartan UltraScale+ FPGA family
by EraYaN on Monday March 11, 2024 @11:01AM
(#39669065)
It has basically always been this way. Xilinx wasn't different before this announcement. Altera wasn't and isn't either. Some of the smaller lattice designs are a bit more open, but are a different market segment.
You will use Vivado and you will like it!
Something "horribly" simple I hope and suppose (memory mapped command ring buffers and dma buffers?)
Then quickly getting up and running a shmol RV64 core... and I guess this is hacker paradise.