PCBs can warp to various amounts post reflow, which can cause all sorts of problems with parallelism between your PCB and sanding surface. You would also be able to mitigate this type of attack by filling vias with conductive epoxy and plating over them, which is a well established process option in PCB fabrication.
Might another way to resolve issues with the PCB dishing be to photograph the layers at a fraction of a layer height? So that in that way you have a lot more slices to work with, and you can digitally "flatten" the PCB?
1. align the image stack. not trivial, but a common task.
2. take several cross-sections, in both dimensions, and have a human draw a line along a specific layer line
3. linearly interpolate these lines into a surface.
4. for each pixel in each output layer, set the value to layers[l + offset][x][y], where the offset was calculated in step 3.
It doesn't seem like this problem requires anything crazy, just traditional computer vision, but of course the devil is in the details.