No. You need to explicitly request the tooling from the for-profit company (Analogue, which wraps Intel/Altera) so that the open source cores you write can run on their closed source hardware. It sounds exactly like the situation with MiSTer, except that there is a second for-profit middleman. Afaik MiSTer cores can't run on open source hardware or compile on open source toolchains.

It's really a matter of taste whether you like Intel more than Intel+Analogue. It's wrong to call MiSTer an open source project but openFPGA not just because the number of for-profit companies needed is different.

Yeah. Open toolchains have come a long way, but they’re not there yet. The Lattice ICE family are the best supported.

You're probably thinking iCE40.

Note ECP5 and Nexus support is similarly good by now, and these families have larger FPGAs better suitable for miSTer cores.

There's now also some support for GW1N/GW2N FPGA families from China. These have the advantage of being relatively quite cheap, and I hear they have FPGAs with 250k+ LBs coming, with RISC-V hard cores built in.

Wow that sounds cool. I'm playing around with the UP5K (pico ice) right now with apio and it's already the dream. With bigger FPGAs the sky would be the limit.

>Afaik MiSTer cores can't run on open source hardware or compile on open source toolchains.

It is on a core-per-core basis e.g. I managed to run some cores on ECP5 as well as GW1N, using open-source synth/route tools.

There's also some effort to make it FPGA family independent.

It is not hopeless; we will get there.