Re:Espressif ESP32: Breaking HW AES with Power Analysis (2023)
by graphe on Saturday February 10, 2024 @01:30AM
(#39324102)
You really learned nothing?
>Therefore, we decided, in similar fashion as Ledger’s scaffold, to make our own custom board where all the relevant signals are routed to dedicated pins.
Explaination or theory: someone else did it the same way.
>Throughout our research we used two acquisition techniques that are supported by our oscilloscope: normal block mode and rapid block mode. We used Picoscope’s Python bindings to communicate with the oscilloscope. We used their ps3000aRapidBlockExample.py as a reference to integrate rapid block mode into Riscure’s FiPy.
Sounds like they used what worked on their hardware.
>Therefore, we decided, in similar fashion as Ledger’s scaffold, to make our own custom board where all the relevant signals are routed to dedicated pins.
Explaination or theory: someone else did it the same way.
>Throughout our research we used two acquisition techniques that are supported by our oscilloscope: normal block mode and rapid block mode. We used Picoscope’s Python bindings to communicate with the oscilloscope. We used their ps3000aRapidBlockExample.py as a reference to integrate rapid block mode into Riscure’s FiPy.
Sounds like they used what worked on their hardware.