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A comment on Show HN: Atopile – Design circuit boards with code.

Re:Show HN: Atopile – Design circuit boards with code by al2o3cr on Monday February 05, 2024 @09:38PM (#39270096)
IMO it's hard to spot the "holes" for parameters in a module - for instance, in the logic-card project the instantiations of "LDOReg" end up setting values of objects in "Vdiv" two abstraction layers down.

https://github.com/Timot05/logic-card/blob/a63581636233dd1f9...

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Re:Show HN: Atopile – Design circuit boards with code by mawildoer on Monday February 05, 2024 @09:41PM (#39270129)
You're right. It definitely is currently.

This is a hole we're planning to fill between linters and a language server. Picture a red-underline under an instance which is insufficiently configured, for example

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