Depends on what you call RISC, I guess: many people would argue that a load-store architecture is a required part of it, and the zero-page is actually an anti-thesis to that. In fact, it hints at the possibility of a memory-memory architecture (no general-purpose registers, minimal amounts of indexing/address registers). Implementations of such architecture could, of course, use whatever amount of hardware registers (unexposed in the instruction set itself) as a memory cache. Throw in some relaxed memory model, e.g. other cores don't see the memory stores via [STACK_REGISTER+offset] unless an explicit flush command is issued, and I imagine the end result will be quite nice to both use from the programmer's point of view (no register allocation!) and from the implementers point of view as well (register allocation is back, but now it's register- and memory-renaming, the latter being simplified by the lax memory model). One of the downsides is that the instruction encoding definitely won't be compact, with all those memory offsets instead of register numbers.
What a fun discussion http://forum.6502.org/viewtopic.php?t=720
The Page 0 addressing mode basically let you use the first page of RAM more or less as 256 extra 8-bit registers (or 128 16-bit registers, etc.), as those locations could be accessed faster and with fewer instruction bytes than locations elsewhere in RAM.
A fair number of languages were implemented on 6502-based machines by using multiple Page 0 locations to simulate wider registers.