IIRC, Intel announced about a year later plans to develop something similar. That being said, at the time they didn't have a specific timeline.

Yes. Kind of.

AMD processors have Upper Address Ignore (UAI) with 7 bits of ancillary data, for Intel there is Linear Address Masking (LAM) with 6 or 15 bits [1]. The latter has made it into Linux after some initial resistance [2].

[1]: https://lwn.net/Articles/888914

[2]: https://www.phoronix.com/news/Intel-LAM-Merged-Linux-6.4

Those sound analogous to the TBI feature in Arm, rather than MTE itself (which uses TBI).

They did, MPX, however the design was buggy and eventually removed.

Currently x86 is the only mainstrem architecture without a plan for hardware memory tagging.

Even RISC-V has an ongoing discussion for hardware memory tagging extensions.

If AMD and Intel drag their feet long enough, CHERI will be production ready before then.

True, however unless Windows developer community finally embraces ARM, that is something that will only worry them on the server with UNIX based workloads.