it seems like everyone settles for ugly, barely usable interfaces like CUDA, OpenCL, and then scabs them over with a higher-level interface like tensorflow.
Now consider that with Phoenix Point APUs you have Zen 4 CPU, memory controllers, IO controller, RDNA3 GPU, and the XDNA "transputer-like" coprocessor, all hanging off common cache coherent transport (Infinity Fabric). All the hardware parts are there.
I think we could argue that tensorflow and/or pytorch has displaced any HSA interest, too. These are programming interfaces that do an OK job of abstracting from the hardware details, and are totally embraced by the most demanding field (AI).
In the wee hours of this morning, I was trying to figure out why my attempts to build LLVM 17.0.3 from source were failing because it couldn't find an HSA-related symbol.
My impression was that the build-system's support for using HSA was a little wonky, but I'm not sure if that's fair. IIRC I worked around the issue by not trying to build LLVM's openmp code.
As caches have gotten bigger I’ve wondered when or if we will treat them as local memory instead of trying to maintain an illusion of cache coherency at a high cost.
But if you never call those, it is possible to access the cache explicitly. Coreboot have a custom in-tree compiler, ROMCC [1] that compiles C to a subset of x86 that never emits memory operations.
They use this to treat cache as RAM [2] for a brief period during early boot before the RAM itself gets initialized.
1. https://github.com/wt/coreboot/tree/master/util/romcc The whole compiler is a single C file
2. https://www.coreboot.org/data/yhlu/cache_as_ram_lb_09142006.... Perform s/LinuxBIOS/Coreboot/ in your head as you read
I have seen a patent application for a technology from {big hardware company} addressing exactly this. Dunno if the approach will work, but there are definitely plans
There's still no real synergy between CPUs and GPUs, even though they get less different with time. No one seems to have a decent plan for how to balance local memory resources with cache-coherency over CXL. Inter-system networking seems to be frozen in 1980 (just with faster serdes). Does in-chip and inter-chip optical change anything, or does it just mean littering the place with tranceivers?