Re:Major Changes at RISC-V Designer SiFive
by kajiryoji on Tuesday October 24, 2023 @03:23PM
(#38004028)
The shift register design sounds quite expensive. You're essentially constructing
<issue width> number of crossbars of 32 times <comparator widths> connected to a bunch of comparators to determine instruction boundary. In a wide design you also need to do this across multiple 32-bit lines
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Re:Major Changes at RISC-V Designer SiFive
by monocasa on Tuesday October 24, 2023 @04:21PM
(#38004904)
Well, half that because the instructions are 16 bit aligned. And approaching half of even that because not every decoder needs access to every offset. Decoder zero doesn't need any. Decoder one only needs two, etc.
But you need most of that anyway because you need to handle program counters that aren't 32 byte aligned, so you need to either do it before hitting the decoders, or afterwards when you're throwing the micro-ops into the issue queues (which are probably much wider and therefore more expensive).