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A comment on Major Changes at RISC-V Designer SiFive. Parent comment

Re:Major Changes at RISC-V Designer SiFive by kajiryoji on Tuesday October 24, 2023 @03:21PM (#38003979)
Haha that'd be a little counterintuitive given all 32-bit aligned is the trivial case for decoding variable length instructions, unless you're thinking about prefetching/branch prediction etc
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Re:Major Changes at RISC-V Designer SiFive by lmm on Tuesday October 24, 2023 @07:03PM (#38006895)
> all 32-bit aligned is the trivial case for decoding variable length instructions

That's the point? You can go faster if everything is 32-bit aligned, i.e. you don't have variable length instructions.

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