Major Changes at RISC-V Designer SiFive

Re:Major Changes at RISC-V Designer SiFive by classichasclass on Tuesday October 24, 2023 @11:09AM (#38000269)

Power10 added "prefixed" instructions, which are effectively 64-bit instructions in two 32-bit halves (the nominal instruction size). They are primarily used for larger immediates and branch displacements.

https://www.talospace.com/2021/04/prefixed-instructions-and-...

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Re:Major Changes at RISC-V Designer SiFive by TanjB on Tuesday October 24, 2023 @12:12PM (#38001251)

MIPS had load const to high or low half. More that 40 years ago Transputer had shift-and-load 8 bit constants. Lots of ancient precedents for rare big constants.

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Re:Major Changes at RISC-V Designer SiFive by classichasclass on Tuesday October 24, 2023 @12:49PM (#38001805)

So does classic PowerPC, SPARC, and many other ISAs. It's the most common way to handle it on RISC. The Power10 prefixed instruction idea just expands on it.

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