TanjB
They don't need perfect silicon. It can be grown on a continuous ribbon which is sliced into panel sizes like they do for solar cells. If they need a perfect surface they can deposit some pure Si to finish it. Maybe we will eventually see that replace ingots for chip grade.
But even during the Dennard era there were a bunch of big random innovations needed to keep things going. CMP allowing the number of metal routing layers to balloon, keeping distances under control. Damascene metals allowing much finer metals carrying heavier currents. Strained channels for higher frequency and better balance between P and N. Work-function-biased fully depleted transistors to avoid the stochastic problems with doping small channels. Etc.
So what really happened is not that Moore ended. We still have a wealth of random improvements (where "wealth" is the driving force) which contribute to an emergent Moore improvement. But the large change is Dennard ended, which gave us scaling at constant power. Although some of the random improvements do improve energy efficiency per unit of computation, they are not overall holding the line on power per cm2. At the end of the classic Dennard we were around 25W /cm2 but now we commonly have 50W in server chips, and there are schemes in the works to use liquid cooling up to hundreds of W / cm2.
Well, ok. But does that kill Moore? Not if it keeps getting cheaper per unit function. And by that I do not mean per transistor. But as long at that SOC in your phone keeps running faster radio, drawing better graphics, understanding your voice, generating 3D audio, etc., and is affordable by hundreds of millions of consumers, Moore remains undead.
The dominant cause of DRAM failures is bit flips from variable retention time (VRT), where the cell fails to hold charge long enough to meet refresh timing. These are believed to be caused by stray charge trapped in gate dielectric, a bit like an accidental NAND, and they can persist for days to months. This is why the latest generation (LPDDR4x, LP/DDR5) have single bit correction built into the DRAM chip. Along with permanent single cell failures due to aging this probably fixes more than 95% of DRAM faults.
The DRAM vendors sure could do a lot better on publishing error statistics. They are probably the least transparent critical technology used in everything, but no regulation requires them to explain and they generally refuse statistics on faults even to major customers (which is why folks like AMD run large experiments at supercomputer sites to investigate, and most clouds gather their own data).
That said, DRAM chips are pretty good. The DDR4 generation probably had better than a 1000 FIT rate per 2GB chip, so in a laptop with 16GB that would have been less than 10 error per million hours, or under 1 per 50 laptops used for a year.
For many of us the vast majority of data is in media files. I personally notice broken photos and videos every now and then. I would love to have a laptop with a competent ECC level, but they do not exist. Even desktop servers often come without. It is unclear how much better the LP/DDR5 generation will be since the on-die ECC still does not fix higher order faults in word lines and other shared structures, which may sum to as much as 10% of aging faults. All simply educated guesses, since the industry will not publish.
The main problem with scaling is that SRAM found an optimal layout in FinFET with no significant wiring issues. While scaling from 7nm on down none of the tricks that benefit logic density - fewer lines, reduced gaps, contacts over active gate - SRAM does not need them. It was already optimal. The only thing it benefits from is honestly finer features, which is happening only slowly.
The next major jump expected is CFET where going vertical is matched by a new optimal pattern that takes advantage if the N and P being above each other. That is generally expected for N2/20A processes.
There were 7 registers to play with. AX, BX, CX, DX, SI, DI, and occasionally BP. MS-DOS had no rules about frame pointer although later Borland would prefer it was kept to a standard use so that exceptions can be handled.
It would have run faster in 32 bit. Many fewer cross products for multiply and faster convergence for division and sqrt, plus just fewer registers needed. But updating the entry and exit code may have been the largest win. By the mid 1990s the FPU was moving onto the CPU chips even at the low end so the main goal would have been stability and backwards compatibility.
I wrote assembly code for many machines before and after that. In the early days such careful juggling of registers was routine. I generally wrote my algorithms in Pascal (later in Modula or Ada and by Borland days, in C++) and then hand compiled down to assembly. That separation of algorithm and coding stopped it getting too tangled.
Thanks for the shout out! These days I write System Verilog (algorithms modelled with C++) for hardware projects, and Julia for the pure software.
Masks are also a significant expense. N5 is an EUV intensive process with $10..20M per set. They probably run through a new mask set every 50,000 wafers or so, and likely need 2 mask sets to get beyond 10,000 (two days) so they can swap them out for inspection and cleaning. So their mask costs for the 100,000 wafers they need are somewhere above $50M.
It is interesting to compare with a project like Graviton2 on N7, which is more like $12k per wafer including test and packaging and likely 120 chips yielded at 4cm2 each. They probably need 2M chips per generation, and as their design is not nearly as aggressive as the A14, with far fewer different functional blocks and mostly off the shelf IP, they may have done it with as little as $200M of R&D. So they can get a G2 for as low as $200, maybe as much as $300. That makes each core $5 or less. About a third the price of the DRAM they need per core.
Excellent insight. CMP and damascene metal (guess who!) really kicked CMOS into top gear.