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A comment on Major Changes at RISC-V Designer SiFive. Parent comment

Re:Major Changes at RISC-V Designer SiFive by rwmj on Tuesday October 24, 2023 @09:44AM (#37999095)
No idea if this is true for Qualcomm, but people from Rivos have also been in that meeting arguing against the C extension and as far as I know Rivos have no in-house Arm cores they are trying to reuse.
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Re:Major Changes at RISC-V Designer SiFive by monocasa on Tuesday October 24, 2023 @09:55AM (#37999233)
Rivos was formed from a bunch of ex-Apple CPU engineers. I'm sure they would feel more comfortable with a closer to AArch64 derived design as well.
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Re:Major Changes at RISC-V Designer SiFive by gchadwick on Tuesday October 24, 2023 @12:23PM (#38001432)
They might also know a bunch of techniques to give high performance that only work if you've got nice 32-bit only aligned instructions!
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Re:Major Changes at RISC-V Designer SiFive by kajiryoji on Tuesday October 24, 2023 @03:21PM (#38003979)
Haha that'd be a little counterintuitive given all 32-bit aligned is the trivial case for decoding variable length instructions, unless you're thinking about prefetching/branch prediction etc
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Re:Major Changes at RISC-V Designer SiFive by lmm on Tuesday October 24, 2023 @07:03PM (#38006895)
> all 32-bit aligned is the trivial case for decoding variable length instructions

That's the point? You can go faster if everything is 32-bit aligned, i.e. you don't have variable length instructions.

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