Major Changes at RISC-V Designer SiFive

Re:Major Changes at RISC-V Designer SiFive by camel-cdr on Tuesday October 24, 2023 @06:36AM (#37997077)

This is basically what qualcomm proposes, 32 bit instructions and 64 bit aligned 64 bit instructions.

I don't think we have real data on it, but I suspect that the negative impact of this would effect 16/32/48/64 way more than just 32/64.

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Re:Major Changes at RISC-V Designer SiFive by londons_explore on Tuesday October 24, 2023 @08:04AM (#37997920)

I would like to also have aligned 16 bit instructions. And maybe even aligned 8 bit instructions for very common things like "decrement register 0" or "test if register 0 is greater than or equal to zero". "Jump back by 10 instructions", etc. Those instructions get widely used in tight loops, so might as well be smaller.

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Re:Major Changes at RISC-V Designer SiFive by adgjlsfhk1 on Tuesday October 24, 2023 @09:00AM (#37998579)

8 bit instructions are a really bad idea. you only get a tiny number of them and they significantly increase decode complexity (and massively reduce the number of larger instructions available)

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