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A comment on The legend of “x86 CPUs decode instructions into RISC form internally”. Parent comment

Re:The legend of “x86 CPUs decode instructions into RISC for... by jeffbee on Sunday June 18, 2023 @12:49PM (#36381907)
The design of RISC-V starts with an entire chapter excoriating MIPS for being useless and impossible to reduce to transistors.
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Re:The legend of “x86 CPUs decode instructions into RISC for... by allenrb on Sunday June 18, 2023 @01:26PM (#36382292)
Some of the same people were involved, no? They must have had a good time writing that. “Things we have learned the hard way”.
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Re:The legend of “x86 CPUs decode instructions into RISC for... by mumbel on Sunday June 18, 2023 @01:53PM (#36382551)
And now MIPS, the company, makes RISC-V
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Re:The legend of “x86 CPUs decode instructions into RISC for... by brucehoult on Sunday June 18, 2023 @08:32PM (#36385956)
Berkeley RISC I and RISC II had register windows, and led to SPARC. MIPS was Stanford.

And, yes, they learned the hard way that register windows are a bad idea. Patterson says they did it because their compiler didn't have as good register allocation as Stanford's compiler.

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