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Re:Render a neural network into CUDA/HIP code by antinucleon on Friday June 02, 2023 @02:06PM (#36168666)
AITemplate's original designer is here. We quit Meta in January and start HippoML (https://hippoml.com/). We just disclosed our new engine's performance on LLM: https://blog.hippoml.com/large-language-model-inference-from... On Apple M2 Max our new engine encode/decode is 13.8X/2.4X faster than llama.cpp
Re:Render a neural network into CUDA/HIP code by mhh__ on Friday June 02, 2023 @02:19PM (#36168828)
Really doesn't surprise me that much. Llama.cpp seems like an OK first passs but I assume there is loads of time left on the table in terms of graph optimizations optimizing for the memory hierarchy properly.
Re:Render a neural network into CUDA/HIP code by brucethemoose2 on Friday June 02, 2023 @02:36PM (#36169008)
It also doesn't use Apple GPUs at all. Its 100% CPU inference, with some CUDA/OpenCL (but no metal) offload at the moment.
Re:Render a neural network into CUDA/HIP code by antinucleon on Friday June 02, 2023 @03:01PM (#36169315)
It is actually non-trivial to get GPU run fast, especially on SoC with strong CPU like M2.
Re:Render a neural network into CUDA/HIP code by hutzlibu on Friday June 02, 2023 @03:49PM (#36169944)
GPU programming in general is definitely not trivial, as I can confirm with struggeling to learn WebGPU right now.

But it really depends on the problem, but simple math operations on lots of data is usually indeed trivially faster. Like AI mostly is with math on matrices.

For example I just implemented a simple 2D raycastsolver in wgsl and as a first project it is totally not optimized - but even on my old laptop with crappy integrated GPU, but (relativly) fast CPU - I can now do 10000 raycasts per frame easily, while the cpu (wasm!) struggles with 500.

The raw power of the gpu is really awesome. But every step is hard and debugging a mess. Which is why only a handful of people seems do be doing it. But now would probably be a good time, to get into it.. as I think gpu compute just has started and will get big.

Re:Render a neural network into CUDA/HIP code by paulmd on Friday June 02, 2023 @05:48PM (#36171228)
I've been out of the space for a long time, and it's possible you know these already, but these are a couple weird tricks that can help:

* Radix sort is your friend. Fun fact, O(n log n) is not the fastest a sort can run, it's the fastest a comparison-based sort can run. Radix sort runs in O(N) time, and in fact parallelizes extremely well on GPUs. Extremely. They are great at it. And there are in-place radix sorts too, just a bit slower (same asymptotic performance tho).

* "Insert an element into this collection" style steps can be replaced by a sort and a prefix-sum operation. If you know the offset of the first element with key K, and you know the offset of the first element with key J, you know the offset and size of that "collection" for K within a flat array ("size(K) = offset(J) - offset(K)"). Both of these run super fast in parallel and if you can tweak your problem around to be some kind of sorting operation that usually produces good speedups like this. Easiest way to get a speedup from everything I've heard.

* Recomputing is often much faster than storing intermediate results. "Procedural generation" is interesting because you can re-compute the generation step on demand. Random123 is also very nice compared to a (CuRand) mersenne twister/etc - why are you, a believer in the cryptographic maxim that hash(key, msg) is uncorrelated to hash(key, msg+1), still storing RNG state? Being able to play back arbitrary parts of a datastream at will is incredibly powerful, you can fastforward and rewind through the data previously used to interact with an item, as long as you know the epoch of the interaction you want for a particular key. And because computation is cheaper than memory, and memory bandwidth - it's really actually practically free in program time terms to just do some math. This is a form of data compression and performance enhancement.

* Generally you must understand the idea of coalescing and divergence and keep those lanes executing. And it is highly preferable to use sorts and scans and butterfly operations (reduction, etc) even within a warp, because traditional "mutex/atomic" paradigms don't work well with 100k threads. But this is just the programming idioms of this particular platform, I am sure LISP is similar too in terms of "oh that's how you do that" once you're accustomed.

* Texture maps aren't just for graphics, they are a black box that lets the GPU perform 2D and 3D coalescing and some interpolation.

* Intelligent use of constants memory is another one, probably as is the use of CPU memory. If a value will be seldom accessed, you can probably stuff it into host memory and just accept the slowdown. Or you can store only epochs on the GPU and recompute intermediate values as needed. Try to ensure that all threads in a warp will do it too (sorting vs recomputing).

* Raytracing is of course impervious to all of this (so don't worry too much that you can't magically hammer a speedup out of it, nobody really can). You can accelerate the raycasting and intersection testing (and AMD and NVIDIA and Intel all do this differently) but as a general matter rays are completely random and uncoalesced. Ray sorting/shader execution reordering is something that needs hardware assistance, and Intel and NVIDIA both have hardware along these lines. The idea of Intel of making a facility for async future/promise dispatch for sparse tasks (and then sorting the shaders to get good coalescing/etc) is really neat and they've said it's going to come to GPGPU. https://youtu.be/SA1yvWs3lHU?t=289

* You can, however, use your rays more efficiently. And that's an area of active focus for everyone. And I think more efficient use of TAAU samples is probably where raster is going too.

Re:Render a neural network into CUDA/HIP code by gregjm on Friday June 02, 2023 @08:58PM (#36172661)
Personally I would lean away from radix sort once the problem size gets too large, on Turing they made the per-SM L1 cache coherent and on Ampere they made L2 cache significantly larger so getting maximum throughput requires more actively designing for cache-friendly access patterns. The access pattern of radix sort will be very strided, so you get low cache utility for those longer distance swaps. If your problem fits into shared memory or even registers (for in-warp shuffles) then definitely, radix sort is super efficient!

Memory coalescing probably got a little more lenient than when you were programming. If any group of threads in a warp is accessing a 128B size-and-aligned region of memory, that’s perfectly matched the 128B line size between L1TEX cache and L2 cache and you get coalesced accesses. Even 32B size-and-aligned (e.g. each pair of threads accesses two halves of a 32B region) isn’t all that bad, since it aligns with the 32B L2 cache line size to global memory. You run the risk of getting poor load/store utility if you don’t access the other 96B in that L1TEX line somewhere in the same block, though.

Constant memory is less important than it used to be, since constant memory goes through the texture memory, and the L1 cache was unified and combined with the texture cache. There’s still an LDG.CONSTANT SASS instruction on Turing, though, so there’s still a difference in the hardware that escapes me right now. IIRC you can write a MOV instruction with the source operand in constant memory (rather than LDG.CONSTANT) which doesn’t put load on the load-store unit (LSU). Could be useful if you’re getting warp stalls due to memory pipe throttling.

Re:Render a neural network into CUDA/HIP code by paulmd on Friday June 02, 2023 @09:12PM (#36172730)
Interesting, love it!

> on Turing they made the per-SM L1 cache coherent and on Ampere they made L2 cache significantly larger

Yeah Turing/Ampere are more than people give them credit for. They are quite a bit more powerful in compute in general iirc, the core is really Volta-descended iirc and not Pascal.

> so getting maximum throughput requires more actively designing for cache-friendly access patterns. The access pattern of radix sort will be very strided, so you get low cache utility for those longer distance swaps. If your problem fits into shared memory or even registers (for in-warp shuffles) then definitely, radix sort is super efficient!

Does dumping warp-sorted data into the buffer help? Eg can each warp or each block sort their output so what they're dumping in can be "galloped", like a partially-sorted mergesort or something? Finding those boundaries between output cells is (ironically) another prefix-scan lol.

Is it just that you need a different sort, or does sorting just not work that well now?

Are prefix-scans still good at all?

Interesting, anything in particular to read about it from Anandtech or Chips+Cheese or what? Or should I just read the whitepapers? (/sigh, reading primary sources, my only weakness)

(I really wish there was an Agner Fog for GPUs!)

> IIRC you can write a MOV instruction with the source operand in constant memory (rather than LDG.CONSTANT) which doesn’t put load on the load-store unit (LSU).

hackerman.jpg

Re:Render a neural network into CUDA/HIP code by gregjm on Monday June 05, 2023 @01:21PM (#36199625)
> Interesting, anything in particular to read about it from Anandtech or Chips+Cheese or what? Or should I just read the whitepapers? (/sigh, reading primary sources, my only weakness)

I haven’t had great luck with consulting non-primary-sources, most of my knowledge comes from reading NVIDIA blog posts and GTC presentations as they become relevant. Lately I’ve been working with CUTLASS and reading through that documentation — maybe start with their presentations and work back through their references? I’ve learned a lot by reading the architecture tuning guides from NVIDIA, too.

> Does dumping warp-sorted data into the buffer help? Eg can each warp or each block sort their output so what they're dumping in can be "galloped", like a partially-sorted mergesort or something? Finding those boundaries between output cells is (ironically) another prefix-scan lol. > > Is it just that you need a different sort, or does sorting just not work that well now?

I’m not sure, honestly! All I know is that recently I’ve been looking at radix sort kernels with lower-than-expected memory throughout and low cache hit rates :)

> Are prefix-scans still good at all?

The CUB linear-time prefix scan kernels seem to be fantastic still, they operate basically at the speed of DRAM with really high compute utilization. When I’ve seen lower-than-expected performance with these kernels, it’s because of an issue with an inefficient transform being made as part of the input/output iterator ranges, or because of some local memory usage due to an indexing operation in a local variable that couldn’t be fully inlined into registers.

Re:Render a neural network into CUDA/HIP code by boywitharupee on Friday June 02, 2023 @03:01PM (#36169316)
zero-copy with mmap was added to llama.cpp, but the way it was implemented sparked controversy.

I'm particularly interested in a specific aspect of the problem. Do you load weights with zero-copy using Metal? MTLIOCommandBuffer offers convenient functions to directly read a file into a MTLBuffer. Which was part of Metal 3 only.

Re:Render a neural network into CUDA/HIP code by fathyb on Friday June 02, 2023 @04:02PM (#36170039)
I think GP meant zero-copy communication with the GPU, eg. through `newBufferWithBytesNoCopy` [0], which is only possible with unified memory architectures, eg. integrated GPUs.

The mmap change was just about mapping the model files in memory instead of copying them, which has less overhead.

[0]: https://developer.apple.com/documentation/metal/mtldevice/14...

Re:Render a neural network into CUDA/HIP code by brucethemoose2 on Friday June 02, 2023 @08:42PM (#36172595)
Yeah this is precisely what I meant. I think it is possible in Vulkan too.

I brought it up because shuffling weights around takes lots of time, takes up more RAM, and saps memory bandwidth the IGP and CPU desparately need.

Re:Render a neural network into CUDA/HIP code by astrange on Saturday June 03, 2023 @02:36AM (#36174288)
> I think GP meant zero-copy communication with the GPU, eg. through `newBufferWithBytesNoCopy` [0], which is only possible with unified memory architectures, eg. integrated GPUs.

It can still be beneficial on discrete GPUs because it avoids a copy inside the driver.

Re:Render a neural network into CUDA/HIP code by huevosabio on Friday June 02, 2023 @02:34PM (#36168994)
Any idea how hippo, AI Template and TVM compare in performance?
Re:Render a neural network into CUDA/HIP code by antinucleon on Friday June 02, 2023 @02:37PM (#36169032)
Hippo is faster than AITemplate, and supports more generative models. We haven't compared vs TVM, but for absolute token/s on M2 Max, Hippo is able to running decoding on LLAMA with datacenter level GPUs (with other SW).
Re:Render a neural network into CUDA/HIP code by huevosabio on Friday June 02, 2023 @03:24PM (#36169627)
Thanks, I've added myself to the waitlist. Please let us know when this can be tried!
Re:Render a neural network into CUDA/HIP code by choppaface on Friday June 02, 2023 @08:31PM (#36172538)
How does Hippo compare with TensorRT?
Re:Render a neural network into CUDA/HIP code by philipturner on Saturday June 03, 2023 @11:45PM (#36182908)
The difference in bandwidth between M2 Max and data centers GPUs isn't that much (less than a factor of 5). The difference in compute is much, much larger. If you only have fast GEMV kernels, and not fast GEMM kernels, you're basically locked into an inference engine that can only run GPT-style transformers efficiently. However, it can *technically* support all the models, but at what ALU utilization?
Re:Render a neural network into CUDA/HIP code by brucethemoose2 on Friday June 02, 2023 @02:16PM (#36168806)
Very interesting.

Is 8bit/4bit support in the works? Will it work with bitsandbytes out of the box? Speedy inference is great, but in practice many users are running the biggest ~4-bit LLM that will fit into their RAM/VRAM pool these days. This is why llama.cpp is so good, its (AFAIK) the only implementation that will split a 4 bit quantized model so easily.

Re:Render a neural network into CUDA/HIP code by antinucleon on Friday June 02, 2023 @02:30PM (#36168936)
Yes. We support >= 1bit <= 16bit models out of box for various of models.
Re:Render a neural network into CUDA/HIP code by ralfd on Friday June 02, 2023 @02:13PM (#36168774)
What is your planned business model here?
Re:Render a neural network into CUDA/HIP code by antinucleon on Friday June 02, 2023 @02:30PM (#36168947)
We will disclose more details very soon.
Re:Render a neural network into CUDA/HIP code by thewataccount on Friday June 02, 2023 @02:49PM (#36169159)
Do you know how it's speed compares to exllama, specifically with an nvidia gpu by chance?
Re:Render a neural network into CUDA/HIP code by antinucleon on Friday June 02, 2023 @03:10PM (#36169437)
We haven't compared yet.
Re:Render a neural network into CUDA/HIP code by yeison on Friday June 02, 2023 @03:04PM (#36169360)
Did Facebook invest in this. Is that why it's under Facebookincubator?
Re:Render a neural network into CUDA/HIP code by antinucleon on Friday June 02, 2023 @03:09PM (#36169429)
We developed AITemplate majorly for Meta's focus at that time, eg Ads/Ranking need. For HippoML is startup we are building for Generative AI. HippoML is not using AITemplate.
Re:Render a neural network into CUDA/HIP code by yeison on Friday June 02, 2023 @03:05PM (#36169384)
Will this have some similarities to what Mojo is trying to solve?
Re:Render a neural network into CUDA/HIP code by antinucleon on Friday June 02, 2023 @03:13PM (#36169483)
Mojo is trying to create a new language to solve the problem, and specialized for CPU. We are using a more pragmatic way to solve GPU AI computation problem.
Re:Render a neural network into CUDA/HIP code by jph00 on Friday June 02, 2023 @06:11PM (#36171467)
Mojo is not at all specialised for CPU. It sits on top of MLIR and excellent support for all major accelerators is planned.
Re:Render a neural network into CUDA/HIP code by philipturner on Saturday June 03, 2023 @11:41PM (#36182885)
For bandwidth-bound problems like large language models, you could also solve it with properly written CPU kernels (Mojo) and usage of the AMX accelerators for compute-intensive parts.

I'd be more interested if they had a GPU port of Stable Diffusion, which is really compute-intensive. That's where the GPU has a major advantage over CPU, on lower-end chips like M1/M2 and M1/M2 Pro.

> specialized for CPU

Mojo's SIMD execution model should map directly to GPUs. Instead of writing shaders thinking about a single GPU thread, you access the assembly ISA directly, thinking about an entire warp/simdgroup. That's how I think when writing SIMD-group matrix kernels anyway.

Re:Render a neural network into CUDA/HIP code by sroussey on Friday June 02, 2023 @05:17PM (#36170859)
Would it work with instructor-xl or similar which is designed for embeddings and retrieval? On device for privacy is key.
Re:Render a neural network into CUDA/HIP code by antinucleon on Friday June 02, 2023 @05:27PM (#36170967)
Yes