> namely anybody can create FREELY a RISC-V microarchitecture AT WORLWIDE SCALE

The problem with this argument is that it ignores the cost of creating the microarchitecture. It’s almost certainly cheaper to license an Arm A series core than to create a comparable RISC-V core from scratch.

Sure we have a firm like SiFive that licenses RV cores to third parties but the existence of firms like Arm and SFive shouldn’t be taken for granted. If rumour has it SiFive were almost taken over by Intel. Thankfully Nvidia were stopped from buying Arm.

If you wish for Arm’s demise you may get the end of their business model and that probably isn’t a great outcome.

risc-v is not limited to sifive, there are several other implementations. And yes, arm and x86 made angry ppl with enough resources to make happen risc-v, and it has been a decade and it is still gaining momentum even if the market is over-saturated with arm and x86. That's last point is really positive, and it allows us to think risc-v could be successful.

But I agree that without _REALLY_ performant implementations, risc-v WILL fail and rumors say that things won't start to get serious before 2024. Nevertheless, in its current state, failure is still a more than valid outcome.

>rumors say that things won't start to get serious before 2024.

What is interesting imho is that they WILL get serious by 2024, including P670, Veyron, Ascalon. All of them seem to implement RVA22 + ratified V.

This is a very fast timeline for RISC-V, which privileged spec was only ratified in 2019.

It all has been happening much faster than even the most optimistic estimates were.

A word of caution: until the "performance" is actually here, better stay humble.

As far as I know and specs wise, RISC-V has been kind of ready for a while, only missing very high performance implementations.

My first real risc-v target is a 100% RV64 assembly keyboard firmware though. Looking at mango pi pro mq boards, but I wish we had 'smaller' RV64 GPIO/USB boards for that, maybe a small GPIO/USB board with a USB block+FPGA with enough gates to instance a small RV64 core.

I see RISC-V as a time bomb.

These are known "detonators" set up for next year. There's more we don't even know of. It is going to happen.

RISC-V is inevitable.

>As far as I know and specs wise

December 2021's batch of extensions done the magic. No hardware out there implements them.

Once it arrives (e.g. Veyron and Ascalon), the thorough disruption of the whole CPU landscape, from microcontrollers to supercomputers, starts.

The acceleration and massive momentum that we've seen to date is nothing compared to what's to come.

I think this may be a bit too many instructions (I did not see hardware accelerated memcpy/memset though). I guess I would use only a small subset of them. Since RISC-V is a royalty free standard, writting directly assembly is worth it, until the abuse of a macro processor and code generation is avoided.

I want to share you optimism, but I advise you to keep your cool. There is a long road to reach the performance of x86/arm microarchitectures (it is harder for risc-v since the "market is over saturated"). And those performant implementations must get access to the best silicium node process... and that...

Veyron and Ascalon's planned releases aren't "IP to license" releases, but actual chips.

Veyron's supposed to have actual server boards on sale late this year.

Ascalon, CPU chiplets and a full AI accelerator product using them, succeeding their current one, which iirc uses SiFive IP.