I understood fast as to do with roadmaps, and used it that way.

Before year end for Veyron, next year for Ascalon. Potentially, there'll be further announcements for performant microarchitectures next year.

As for performance, with Ascalon promising similar to Zen5 performance at significantly reduced power consumption, I don't think there's much reason for concern: Very performant RISC-V microarchitectures are coming.

With all these companies and their strong teams working on new RISC-V microarchitectures, there'll be plenty of choice, soon.

I am always cautious about this. Very. You have those horrible compilers in the way.

I still dunno on which risc-v microarchitecture I'll start coding assembly (wanted to start on the mango mq pro something for a keyboard firmware 100% 64bits risc-v). Finally starting to get rid of those pesky compilers and system language syntax which are unable to be stable on the long run. At best, we'll get very high level language interpreter directly written in risc-v assembly. Just need to be very cautious about macro processor usage.

I started to code some core functions directly in x86_64, and I know it is only a transition phase towards risc-v 64bits ISA (porting from 1 modern ISA to another is still much, much, less work than to code from scratch). I'll enjoy the additional register space (even with a more register space consuming load/store ISA).

BTW, we still missing hardware instruction for direct memcpy/memset/memcmp in risc-v, that said I don't know if that will be pertinent in the end.

Very good to hear, especially if it is open source and performs well (low latency and low jitter).

Ofc, this firmware would be bare metal. Not jocking around. For the moment, I am a bit scared at porting to human assembly the SOC and board init code.

The only non-open source programs I know of are elf/linux video games and the steam client.