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Re:ARM or x86? ISA Doesn’t Matter by immibis on Monday May 15, 2023 @07:23AM (#35946453)
They already do this. The core has 4 or 5 decoders that work in parallel to decode up to 16 instruction bytes, and only the first one can handle more complex instructions. If there is a complex instruction after the first slot in the byte chunk, it realigns the instruction stream (how's that for technobabble?) so the first decoder gets the complex instruction in the next cycle.

This means to exploit your processor's full decode performance you have to reorder your instructions so the complex ones are the first in each 16-byte group, or something like that.

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