Re:ARM or x86? ISA Doesn’t Matter
by Findecanor on Monday May 15, 2023 @07:36AM
(#35946573)
I think the parent poster might have been referring to the integer multiply-add instruction.
In fact, 64-bit ARM does not have a regular MUL instruction. "MUL" is an alias to a MADD with the zero register as addend.
Flipping one parameter bit in the instruction word changes a MADD into a MSUB. That instruction is used to compute the remainder after a division. Bigger ARM cores (such as Apple M1) perform macro-op fusion of DIV and MSUB to deliver both quotient and remainder in one operation.
Anyway. I thought that was pretty clever by ARM's designers.
Fused multiply-add is (https://en.m.wikipedia.org/wiki/Multiply%E2%80%93accumulate_...) is extremely useful and part of IEEE754-2008.
Because of that, it would surprise me if a modern CPU with floating point wouldn’t have it.
> And RISC-V uses 6 bytes because of shortened instruction for addition
That Wikipedia page claims RISC-V has fused multiply-add, so that may be compiler inefficiency. An answer to https://stackoverflow.com/questions/57248403/why-fused-multi... says gcc can generate it at -O3)