For (semi) fixed pipeline operations FPGAs will basically always be worse than some slightly more specialized ASIC like a GPU/AI engine.
One area FPGAs can be exceptionally good at is real-time operations. You have much better control over timing in the general on FPGAs vs MCU/CPUs, but I don't think that's inherent (you could probably alter the mcu architecture a bit and close the gap).
I could be wrong but I also think you get better power draw for things like mid to low volume glue chips in embedded systems because you're not powering big SRAM banks and DMAs just to pipe data between a couple hardware interfaces. This is only because of market forces though obviously, because if mid to low volume ASICs become viable in terms of dev time they'll be much better.
Pipelining on an FPGA requires being able to find, and fill, spatial duplication of the operations being done. If you've got conditional operations in a pipeline, now your pipeline isn't so full anymore, and this hurts performance on an FPGA far more than on a CPU (which spends a lot of power trying to keep its pipelines full). But needing to keep the pipelines spatially connected also means you have to be able to find a physical connection between the two stages of a pipeline, and the physical length of that connection also imposes limitations on the frequency you can run the FPGA at.
If you care about FLOPS (or throughput in general), the problem with FPGAs is that they are running at a clock speed about a tenth of a CPU. This requires a 10x improvement in performance just to stand still; given that software development for FPGAs requires essentially a completely different mindset than for CPUs or even GPUs, it's not common to have use cases that work well on FPGAs.
(I should say that a lot of my information about programming FPGAs comes from ex-FPGA developers, and the "ex-" part will certainly have its own form of bias in these opinions).