It would've been cray-cray to boot them from a single board with extra flash via SWD. Does anyone know how fast the RP2040 SWD clock can be driven on a Pico soldered to a central board? How many DMA channels and PIO state machines would be required to build an even faster remote memory access interface? Can a central 9th RP2040 serve as fast RDMA router for 8 other Pico boards? So many unanswered questions ;-).

One way the RP2040 really punches above his price class is internal bandwidth. It has four AHB-Lite bus masters (two M0+ cores with one read-write port, and the DMA engine with a read and a write port) connected a full crossbar switch. There are six SRAM banks of which the four largest are commonly used word interleaved, but can if you want full control over memory timing and bandwidth you can use the uninterleaved alias instead. Most chips priced around a RP2040 (and the SPI flash to go with it) have only a single small SRAM bank. I've found the DMA engine surprisingly pleasant to work with (easy to understand, no fixed request routing to fight, but still very flexible which can save a lot of interrupts). Whoever designed the combination of the PIO channel I/O coprocessors and this DMA engine had a clever tinkers mind. I have to stop myself from wasting time looking for ways to save CPU cycles with trickery that only makes the code hardware to maintain.