AMD and Jedec Are Collaborating on DDR5 MRDIMMs at a Blistering 17,600 MT/S

Re:AMD and Jedec Are Collaborating on DDR5 MRDIMMs at a Blis... by mateja on Thursday April 06, 2023 @04:55AM (#35465928)

CMOS and DRAM are completely different processes and cannot be integrated on the same wafer. This has been tried many times unsuccessfully. This is why you see highly integrated packaging solutions like chiplets. These solutions integrate CMOS and DRAM in the same package, not on the same die.

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Re:AMD and Jedec Are Collaborating on DDR5 MRDIMMs at a Blis... by ilyt on Thursday April 06, 2023 @10:47AM (#35469024)

Chiplets are also used for that, sure (stuff like radios are occasionally separate chiplet made in different process), but I think main push is smaller chips = higher yields

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Re:AMD and Jedec Are Collaborating on DDR5 MRDIMMs at a Blis... by yazaddaruvala on Thursday April 06, 2023 @03:28PM (#35473223)

Thanks, this is what I'd love to understand better.

At the highest level isn't it all EUV? Why can't the laser print both patterns onto the wafer?

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Re:AMD and Jedec Are Collaborating on DDR5 MRDIMMs at a Blis... by realjhol on Friday April 07, 2023 @04:06AM (#35479361)

A CMOS chip doesn't contain any capacitors. DRAM is made of capacitors, and thus has a radically different structure.

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