Verilog Ethernet: Work-in-Progress 100BASE-TX PHY

Re:Verilog Ethernet: Work-in-Progress 100BASE-TX PHY by stephen_g on Friday March 17, 2023 @10:22AM (#35197485)

But if you have IO fast enough to do direct 100Mbps Ethernet, you can do GMII or RGMII to a gigabit PHY (or a parallel to serial converter to talk to an SFP). I think the project here goes through MII internally anyway (I only skimmed it) so it would actually take more space on the FPGA fabric than using a PHY…

So apart from being fun, maybe the main benefit would be less board space because it doesn’t need the PHY chip? (But also potentially lots of disadvantages practically).

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Re:Verilog Ethernet: Work-in-Progress 100BASE-TX PHY by NovemberWhiskey on Friday March 17, 2023 @11:22AM (#35198229)

Yeah. A Fast Ethernet PHY that does 10/100 Ethernet with auto-negotiation, auto-MDI/MDIX etc. is less than $1 in quantity and fits in a footprint a couple of mm on each side.

I think this is a "because I can" sort of thing.

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