Re:Verilog Ethernet: Work-in-Progress 100BASE-TX PHY
by aix1 on Friday March 17, 2023 @05:14AM
(#35194836)
GigE not being achievable on low-end FPGAs explains it really well, thank you.
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Re:Verilog Ethernet: Work-in-Progress 100BASE-TX PHY
by lnsru on Friday March 17, 2023 @06:21AM
(#35195197)
At the moment I have Artix 7 with ancient gigabit PHY running GigE. In Xilinx eco-system it is pretty low-end device.
Re:Verilog Ethernet: Work-in-Progress 100BASE-TX PHY
by stas2k on Friday March 17, 2023 @08:51AM
(#35196433)
20 Euro Colorlight 5A FPGA boards from Aliexpress come with dual Gigabit Ethernet ports, open toolchain to build a SoC that can access them as well.
LiteX allows me to use it as a Gigabit Ethernet powered logic analyzer with a lot of inputs.
Re:Verilog Ethernet: Work-in-Progress 100BASE-TX PHY
by stephen_g on Friday March 17, 2023 @10:25AM
(#35197522)
No, if the FPGA can do this, then it would be perfectly capable of interfacing to a gigabit PHY or a parallel/serial converter for a Gigabit SFP.
Re:Verilog Ethernet: Work-in-Progress 100BASE-TX PHY
by NovemberWhiskey on Friday March 17, 2023 @11:31AM
(#35198371)
RGMII only requires a 125MHz clock; which is not particularly fast. It depends what you mean by "low-end", but you can certainly implement gigabit Ethernet on something like an Intel/Altera MAX 10 for example. It does rather depend on what you want to do with it though.