Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice Lake

Re:Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice... by ryao on Thursday January 05, 2023 @08:42PM (#34269846)

Using the RISC-V V vector instructions means that the underlying hardware vector width can change and the code will automatically take advantage of the larger width.

That said, many of the avx512 instructions are simply extended width AVX2/avx2 instructions. The interesting things about it are really the increased width and the additional registers. Not many of the new instructions that are not bitwidtg extended versions of the old ones are particularly interesting since Intel had already implemented most of the interesting things for smaller vector widths.

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Re:Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice... by kolbe on Thursday January 05, 2023 @09:52PM (#34270363)

I've only scratched the surface of the avx512 instructions, but they are much more broad and useful. Masked gather, scatter, double precision exp and mantissa extraction, and floating point to integer conversions are all new and all proving useful to me.

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