Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice Lake

Re:Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice... by chris6f on Thursday January 05, 2023 @08:41PM (#34269839)

Vector length agnostic programming has its own share of problems. I'm not familiar with the RISC-V V extension, but I assume it's similar to ARM's SVE. There's a good critical look at SVE and VLA here: https://gist.github.com/zingaburga/805669eb891c820bd220418ee...

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Re:Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice... by snvzz on Friday January 06, 2023 @12:38AM (#34271402)

V extension and SVE2 are very different.

Here is a quite recent introduction to RISC-V Vector[0].

0. https://erikexplores.substack.com/p/grokking-risc-v-vector-p...

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Re:Transcoding Unicode with AVX-512: AMD Zen 4 vs. Intel Ice... by janwas on Friday January 06, 2023 @04:03AM (#34272577)

I'm curious why you say they are very different? From where I sit, RVV also supports mask-like predication, and adds two concepts: LMUL (in-HW unrolling of each instruction) plus the ability to limit operations to a given number of elements.

The former is nifty, though intended for single-issue machines, and the latter seems redundant because masks can also do that.

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