By that I mean that when you leave, say, your upstream device and run the traces to downstream, you need to have them come out in the same order: if you start with _P on the left and _N on the right, you want to end that way. A swapover is annoying at USB 2 480Mbps speeds and utterly awful at 20Gbps. (There is also a >50% chance that you miswired the thing and are wiring _P to _N, which increases to >99% if the routing came out naturally neat, but that's just Murphy's Law in action.) It's so difficult and awful to deal with this stuff that USB 3 took a page from Gigabit Ethernet and usually features transceivers that just figure it out: they know you have eight wires in four pairs between eight pins and they can work with that.
Once you have that feature, and transceivers definitely do, there is no point whatsoever in trying to make superfluous changes at the connector bit.
Would the splits and merges definitely make the signal integrity worse to the point that it wouldn't work? Maybe not. But if you're designing a high speed cutting edge standard, you probably don't want to make decisions that limit the best signal integrity an implementer could achieve. Signal integrity is all about balancing the bad SI decisions you have to make because of some product goal or whatever with tighter tolerances elsewhere. The more "clean" the standard is, the more tolerance it has for the implementers.
> Having one of the pins not connect to your processor would create a stub inherent in the design, which is probably a bad idea.
I was more thinking that each wire for a lane has two pins, one on the top and one on the bottom, which are electrically connected. So e.g. SSRX1+ on the top would be connected to SSRX1+ on the bottom, SSRX1- on the top with SSRX1- on the bottom, same for SSRX2+, -, etc.
With the same wiring in the plug as well as in the socket, there wouldn't be any disconnected pins. The wire for e.g. SSRX1+ would split before the plug, then lead to two pins in the plug; the plug connects to two matching pins in the socket which merge back into a single wire.
So in that modified header one differential pair would occupy four pins, two in the top row and two in the mirrored bottom row.
This means the header would have 4 additional pins per row (so 8 in total) compared to what it has now.
But of course the splits and merges in the wire might cause interference as well.