I don't think there's anything AMD-exclusive about cache stacking. It's made possible with TSV (through-silicon via) and direct bonding (ultrasonic or Cu-Cu bonding) to make the movement energy very low. You just bond the second die into some via you've left in your main die, it's relatively straightforward, just an evolution of the same HBM/HBM2 principles but with cache instead.

Going forward there will also be non-cache (and non-memory!) things bonded as well.