Re:AMD, Intel, and Nvidia Reportedly Slash Orders with TSMC
by zorgmonkey on Friday December 30, 2022 @05:00PM
(#34190606)
> It is somewhat harder to make the above on smaller nodes than it is to make just processing cores or just memory.
I'm not convinced this is the reason because the microcontrollers I know of use SRAM not DRAM and SRAM is what CPU caches are (plus of course some extra logic for the cache management aspect). I am aware that designing dense and power efficient SRAM for a cell library is considered a pretty hard thing to do, but it seemingly has already been for modern processes.
I'm not convinced this is the reason because the microcontrollers I know of use SRAM not DRAM and SRAM is what CPU caches are (plus of course some extra logic for the cache management aspect). I am aware that designing dense and power efficient SRAM for a cell library is considered a pretty hard thing to do, but it seemingly has already been for modern processes.