In a similar article we discussed a ring structure to store data. You could store about an L1 cache’s worth of data in a loop that’s roughly a nanosecond long.

Problem we didn’t discuss is this: L1 cache is less than 1/3ns on high end hardware, meaning that L1 caches currently have about 1/3 the latency of this light loop.

Once this doubles or triples again you might have a solution for L2 cache though, since chip clock cycles are relatively stuck.