This core is targeted at "smaller-is-better" applications with few actual instruction-throughput requirements. If it reaches 200 MHz on a Xilinx KU060, I will be delighted. (That specific clock frequency on that specific part carries heavy hints about what this core is intended for.)

With that in mind: the single instruction-per-clock design is for simplicity's sake, not performance's sake. If the execution stage were pipelined, it'd be a different core. If performance is the goal, I'd start by ripping out some of the details that distinguish this core from other (excellent) RISC-V cores.

KU060 costs a nice sum of £4,529.10 on Mouser (out of stock of course)

> out of stock of course

I picked probably the worst time imaginable to get into FPGAs. All of my "higher" end stuff is repurposed mining hardware...

That is actually a good time, because some of it can get super expensive. Also the mining ones just end up in landfills if nobody buys them.

Mining landfills is the way. Future generations will not believe how much magic we threw away.

A fully space-qualified version is something like $150k.

Poor man's Tile64?

> 200 MHz on a Xilinx KU060

> (That specific clock frequency on that specific part carries heavy hints about what this core is intended for.)

Fun clue! Looks like the Xilinx KU060 is a rad-hard FPGA for space applications. Does anyone know what 200 MHz might imply? Comms maybe?