In a similar vein you could turn

  a == 0 || b == 0 || c == 0

into

  !(a && b && c).

If we don't need short-circuit evaluation of b == 0 and c == 0 (which the article assumes), we can turn this into

  !(a & b & c)

which yields similar assembly (n + 1 instructions without branches):

  R0 <- and Ra Rb
  R1 <- and R0 Rc
  R2 <- not R1

Would make an interesting benchmark.