LTT has a video where they tried to see how many PCIe riser cables they could string together before it stopped working.[1] They got to several meters. Maybe you could argue that it's worse inside a PC case since there's more EMI, but it seems like your PCIe riser cable would have to be very out of spec before you'd notice anything.

[1] https://www.youtube.com/watch?v=q5xvwPa3r7M

I wonder if that benchmark actually loaded the PCIe bus to any significant degree after the initial benchmark startup, or just updated a couple small parameters on a single scene and thus mainly just tested the local computation on the GPU?

You'd want to somehow monitor the PCIe bus error rate - with a marginal signal and lots of errors -> retries, something that loads the bus harder (loading new textures etc) could suffer way more.

They do briefly show a different PCIe riser made out of generic ribbon cable [1, 3:27], and say that one failed after chaining only two ~200mm lengths. The quality of the riser cable certainly matters.

[1] https://youtu.be/q5xvwPa3r7M?t=207

You need Steve for that kind of testing, LTT would be busy putting rgb on it and then (badly) water cooling it so they could sell you a backpack with no warranty.

It's not clear whether they reached a limit of drive strength or latency (I doubt EMI is the factor, since he said those are shielded) but that's a good demonstration of the resiliency of self-clocked differential serial (and aggregated serial) buses. The technology is much closer to networking standards like Ethernet than traditional parallel PCI, with features like built-in checksums, error correction (newer versions), and automatic retransmit.

>2017

The 650 Ti is PCIe 3.0. PCIe 4.0 doubles the bandwidth. PCIe 5.0 doubles the bandwidth again. The RTX 40 series GPUs still use PCIe 4.0, which have commonly available conformant riser cables. I suspect the story for PCIe 5.0 will be different.

Oh yeah, I've actually seen that video. I guess I have no reason to be even slightly paranoid!