Re:GeForce RTX 40 Series
by paulmd on Tuesday September 20, 2022 @05:45PM
(#32918215)
Dennard Scaling/MOSFET Scaling is over and it's starting to really bite. Power-per-transistor still goes down, but density is going up faster. Meaning an equal-sized chip on an old node vs a new node... the power goes up on the newer chip.
Physics is telling you that you need to let the chip "shrink" when you shrink. If you keep piling on more transistors (by keeping the chip the same size) then the power goes up. That's how it works now. If you make the chip even bigger... it goes up a lot. And NVIDIA is increasing transistor count by 2.6x here.
Efficiency (perf/w) is still going up significantly, but the chip also pulls more power on top of being more efficient. If that's not acceptable for your use-case, then you'll have to accept smaller chips and slower generational progress. The 4070 and 4060 will still exist if you absolutely don't want to go above 200W. Or you can buy the bigger chips and underclock them (setting a power limit is like two clicks) and run them in the efficiency sweet spot.
But, everyone always complains about "NVIDIA won't make big chips, why are they selling small chips at a big-chip price" and now they've finally gone and done a big chip on a modern node, and people are still finding reasons to complain about it. This is what a high-density 600mm2 chip on TSMC N5P running at competitive clockrates looks like, it's a property of the node and not anything in particular that NVIDIA has done here.
AMD's chips are on the same node and will be pretty spicy too - rumors are around 400W, for a slightly smaller chip. Again, TDP being more or less a property of the chip size and the node[0], that's what you'd expect. For a given library and frequency and assuming "average" transistor activity: transistor count determines die size, and die size determines TDP. You need to improve performance-per-transistor and that's no longer easy.
[0] an oversimplification ofc but still
That's the whole point of DLSS/XeSS/Streamline/potentially a DirectX API, get more performance-per-transistor by adding an accelerator unit which "punches above its weight" in some applicable task and pushes the perf/t curve upwards. But, people have whined nonstop about that since day 1 because using inference is a conspiracy from Big GPU to sell more tensor cores, or something, I guess. Surely there is some obvious solution to TAAU sample weighting that doesn't need inference, and it's just that every academic and programmer in the field has agreed not to talk about it for the last 20 years, right?
Physics is telling you that you need to let the chip "shrink" when you shrink. If you keep piling on more transistors (by keeping the chip the same size) then the power goes up. That's how it works now. If you make the chip even bigger... it goes up a lot. And NVIDIA is increasing transistor count by 2.6x here.
Efficiency (perf/w) is still going up significantly, but the chip also pulls more power on top of being more efficient. If that's not acceptable for your use-case, then you'll have to accept smaller chips and slower generational progress. The 4070 and 4060 will still exist if you absolutely don't want to go above 200W. Or you can buy the bigger chips and underclock them (setting a power limit is like two clicks) and run them in the efficiency sweet spot.
But, everyone always complains about "NVIDIA won't make big chips, why are they selling small chips at a big-chip price" and now they've finally gone and done a big chip on a modern node, and people are still finding reasons to complain about it. This is what a high-density 600mm2 chip on TSMC N5P running at competitive clockrates looks like, it's a property of the node and not anything in particular that NVIDIA has done here.
AMD's chips are on the same node and will be pretty spicy too - rumors are around 400W, for a slightly smaller chip. Again, TDP being more or less a property of the chip size and the node[0], that's what you'd expect. For a given library and frequency and assuming "average" transistor activity: transistor count determines die size, and die size determines TDP. You need to improve performance-per-transistor and that's no longer easy.
[0] an oversimplification ofc but still
That's the whole point of DLSS/XeSS/Streamline/potentially a DirectX API, get more performance-per-transistor by adding an accelerator unit which "punches above its weight" in some applicable task and pushes the perf/t curve upwards. But, people have whined nonstop about that since day 1 because using inference is a conspiracy from Big GPU to sell more tensor cores, or something, I guess. Surely there is some obvious solution to TAAU sample weighting that doesn't need inference, and it's just that every academic and programmer in the field has agreed not to talk about it for the last 20 years, right?