> Note that these instructions are neither documented nor supported by Apple.

What does that mean? Someone pointed out below Apple ships accelerate framework as a higher level supported mechanism to use these instructions?

Intel/AMD have been always good at documenting most of their stuff so perhaps we will see proper supported ones whenever Intel ships it.

I think they mean that using the raw instructions is unsupported and undocumented, officially you have to use the libraries as the interface to them.

Though in reality nobody is stopping you from using those undocumented instructions. If Apple’s Accelerate framework can use it so do you. (Or is it against the EULA?…) There is a slim chance that the behavior of these instructions might change with a software (if Apple is doing any kind of microcode update), but I kinda doubt it.

They've had something similar off-core with GNA since 2019 10th gen Ice Lake for low-power always-on inference use-cases.

Hasn't Intel been shipping scalar instructions for more than a decade?

You’re probably thinking of AVX, Advanced Vector Extensions. That’s a family of vector extensions that has been out for just over a decade (2011). This is about AMX, Advanced Matrix Extensions. AMX is, as the name implies, built around 2D INT8/BF16 matrices (not “1D” FP16/32/64 vectors). It’s not on silicon available to the public.

Also not to be be confused with VMX (AltiVec/Velocity Engine), which predates AVX by another decade or so.

To keep the record straight, we have: 1. AMX, 2. AVX, and 3. VMX.

There’s also Intel VMX, the Virtual Machine Extensions ;) Sometimes it’s referred to as VT-x.

Intel's AMX specifically hasn't yet shipped, but will be coming with their new Sapphire Rapids Xeon chips this year.

*Next year (potentially).

Sapphire rapids might well end up only shipping in Aurora and then being replaced immediately by it's successor.