Re:RISC-V is getting MSIs
by toast0 on Thursday June 30, 2022 @07:18PM
(#31939967)
Note that using the existing data connection (PCI-e is point to point, not a bus anymore) helps solve some race conditions. DMA writes from a device to memory may be buffered by bridges, but interrupt pins are likely not; so if the device wrote to memory and signals that to the host via an interrupt pin, the interrupt may arrive before the write. A message signaled interrupt uses the same mechanism as the DMA write, if the DMA write is buffered, the interrupt write will wait behind it.
[ Parent
| on HN ]
There are no comments on this comment yet.