A lot of Apple’s advantage here comes from the regular instruction size, the relaxed memory semantics, and how those allow efficient instruction reordering.
Not saying x86 can’t ever replicate that, but the ISA makes it harder.
Yep, that's rumoured to be the plan for Zen 5:
https://www.youtube.com/watch?v=dE9N95uSqHA
They have a patent for something similar at least: https://wccftech.com/amd-big-little-processor-cores-show-up-...