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A comment on India reveals RISC-V CPU roadmap, expects product by 2023. Parent comment

Re:India reveals RISC-V CPU roadmap, expects product by 2023 by avianes on Tuesday May 03, 2022 @11:44AM (#31249707)
> lot of the design rides on "oh we're just going to combine all the very RISC instructions into macro-ops to catch up to what ARM is doing"

There are more macro-op fusion suggestions for RISC-V precisely because RV instructions are simple. This gives more opportunity for macro-op fusion.

> so it's not clear if this is even feasible

What macro-op-fusion are you talking about exactly? Most of the macro-op-fusion suggested are quite trivial and have already been implemented

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Re:India reveals RISC-V CPU roadmap, expects product by 2023 by kragen on Tuesday May 03, 2022 @12:06PM (#31249976)
> Most of the macro-op-fusion suggested are quite trivial and have already been implemented

In which chips, and how much of a win are they?

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Re:India reveals RISC-V CPU roadmap, expects product by 2023 by avianes on Tuesday May 03, 2022 @07:18PM (#31254838)
I talk about feasibility, not about design win in a high perf. circuit, since there is no real high perf. RISC-V today and since it's the feasibility that is questioned by the parent.

I can't say if the macro-op fusion will be enough to beat ARM & x86, but I can tell it's feasible.

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Re:India reveals RISC-V CPU roadmap, expects product by 2023 by kragen on Tuesday May 03, 2022 @07:53PM (#31255140)
What do you mean by "implemented"?

Clearly macro-op fusion is a computable transformation of the instruction stream, so macro-op fusion is certainly feasible. I think what Jha was questioning was whether catching up to ARM is feasible if your main weapon is macro-op fusion. The Celio/Dabbelt/Patterson/Asanović tech report I linked yesterday shows that it's promising, but it's been six years and I'd like to know if that's actually being tried and how well it works.

Bruce Hoult's comment from a few months ago suggests that it wasn't really being tried at SiFive, but he left SiFive a couple years ago and might be out of date, and the Honey Badger designs are potentially a whole new ballgame.

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Re:India reveals RISC-V CPU roadmap, expects product by 2023 by avianes on Tuesday May 03, 2022 @08:33PM (#31255445)
> I think what Jha was questioning was whether catching up to ARM is feasible if your main weapon is macro-op fusion.

I don't think so, there are indeed unrealistic macro-op fusion patterns that can reasonably be described as "unfeasible" or "unrealistic".

But macro-op fusion patterns suggested in the RISC-V spec, papers about macro-op fusion on RISC-V, and the SiFive patent on macro-op fusion are realistic and feasible.

> Bruce Hoult's comment from a few months ago suggests that it wasn't really being tried at SiFive

Commits from SiFive people's in GCC [1] suggest that short-forward-branch macro-op fusion patterns are recognized by SiFive hardware.

I don't know if they recognize other macro-op fusion patterns.

But SiFive has a bunch of stuff to improve before diving into macro-op fusion.

[1]: https://patchwork.ozlabs.org/project/gcc/patch/2019043023474...

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Re:India reveals RISC-V CPU roadmap, expects product by 2023 by kragen on Thursday May 05, 2022 @05:51PM (#31278769)
Yes, that's the macro-op fusion pattern Hoult said they were recognizing in his post.
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