Re:India reveals RISC-V CPU roadmap, expects product by 2023
by avianes on Tuesday May 03, 2022 @08:33PM
(#31255445)
> I think what Jha was questioning was whether catching up to ARM is feasible if your main weapon is macro-op fusion.
I don't think so, there are indeed unrealistic macro-op fusion patterns that can reasonably be described as "unfeasible" or "unrealistic".
But macro-op fusion patterns suggested in the RISC-V spec, papers about macro-op fusion on RISC-V, and the SiFive patent on macro-op fusion are realistic and feasible.
> Bruce Hoult's comment from a few months ago suggests that it wasn't really being tried at SiFive
Commits from SiFive people's in GCC [1] suggest that short-forward-branch macro-op fusion patterns are recognized by SiFive hardware.
I don't know if they recognize other macro-op fusion patterns.
But SiFive has a bunch of stuff to improve before diving into macro-op fusion.
I don't think so, there are indeed unrealistic macro-op fusion patterns that can reasonably be described as "unfeasible" or "unrealistic".
But macro-op fusion patterns suggested in the RISC-V spec, papers about macro-op fusion on RISC-V, and the SiFive patent on macro-op fusion are realistic and feasible.
> Bruce Hoult's comment from a few months ago suggests that it wasn't really being tried at SiFive
Commits from SiFive people's in GCC [1] suggest that short-forward-branch macro-op fusion patterns are recognized by SiFive hardware.
I don't know if they recognize other macro-op fusion patterns.
But SiFive has a bunch of stuff to improve before diving into macro-op fusion.
[1]: https://patchwork.ozlabs.org/project/gcc/patch/2019043023474...