Re:The x86 architecture is the weirdo (2004)
by phamilton on Tuesday April 19, 2022 @04:23PM
(#31088525)
To what extent is the decoding consistent? It always felt weird to me that we'd do something in hardware on every execution that could be done once in software at compile time. But if the decoder does smart things that would make more sense to me. For example, with SMT the decoder could choose not to use certain ops if the compute units are in use by the other thread.
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Re:The x86 architecture is the weirdo (2004)
by astrange on Tuesday April 19, 2022 @08:12PM
(#31091119)
That post isn't true, common instructions only take a few µops (or even one) and the main difference is register renaming. Microcoding mainly lets them support old and very complicated instructions that nobody actually needs to be fast.
You can see instruction latencies at https://www.agner.org/optimize/.
Re:The x86 architecture is the weirdo (2004)
by buildbot on Tuesday April 19, 2022 @04:36PM
(#31088715)
I am not sure of any arch that does this, but having a second stage decode buys 2 things off the top of my head - better instruction cache usage, esp. for small loops, and the flexibility to decode ops differently on different versions of the same arch from one binary. Otherwise you would have to have tons of different versions for each flavor of x86 out there.
Re:The x86 architecture is the weirdo (2004)
by imtringued on Tuesday April 19, 2022 @06:32PM
(#31090236)
Intel and AMD CPUs have micro op caches for tight loops.
Re:The x86 architecture is the weirdo (2004)
by akira2501 on Tuesday April 19, 2022 @06:05PM
(#31089912)
> on every execution that could be done once in software at compile time
Which is to me, essentially, VLIW. Those architectures didn't work out very well. There's a lot of memory pressure just to move instructions around and the costs didn't seem to outweigh the benefits.
Re:The x86 architecture is the weirdo (2004)
by phamilton on Tuesday April 19, 2022 @10:35PM
(#31092146)
The Mill CPU and architecture is a fascinating approach here. Who knows if we'll ever see a real piece of hardware from them, but as I understand it they require a compiler tuned to the exact cpu model to maximize on-die memory and other aspects.