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A comment on MIPS provides highly scalable RISC processor IP. Parent comment

Re:MIPS provides highly scalable RISC processor IP by yjftsjthsd-h on Thursday April 07, 2022 @12:25AM (#30940597)
Those are versions of the same(ish) ISA and are (usually?) backwards compatible. I'd mind less if MIPS-the-company made CPUs that were RISC-V with a MIPS-the-ISA compatibility mode, or otherwise actually had continuity; it's the apparent plan to throw away the ISA but keep the name that's jarring.
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Re:MIPS provides highly scalable RISC processor IP by dragontamer on Thursday April 07, 2022 @12:58AM (#30940761)
ARM Cortex M0+ looks nothing like ARM v8.

ARM Cortex M0+ has more similarities with the ATTiny84 / Arduino chips than with cellphone-sized ARMs.

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Re:MIPS provides highly scalable RISC processor IP by pajko on Thursday April 07, 2022 @11:47AM (#30946110)
Cortex M0+ is ARMv6-M. ARMv8 has also an M variant, Cortex M33 is ARMv8-M mainline. ARMv6-M and ARMv8-M have quite a lot of things in common, as v8 is a superset of v6. Or did you mean ARMv8-A? Well, ARMv8-A and ARMv8-M are not compatible intentionally, as the the A variant is strictly 64-bit (some implementations support AArch32 though) and the support for thumb instruction set has been dropped.
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Re:MIPS provides highly scalable RISC processor IP by GoblinSlayer on Thursday April 07, 2022 @04:47AM (#30942141)
That's reasonable: RISC-V is mostly a cleaned up MIPS, so can definitely go as a MIPS family ISA.
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Re:MIPS provides highly scalable RISC processor IP by pajko on Thursday April 07, 2022 @11:35AM (#30945884)
MIPS is as cleaned up as needs to be. RISC-V removed important features and adds loads of bloats via extensions.
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