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Re:Verilog Is Weird by fargle on Wednesday March 23, 2022 @11:35PM (#30786162)
> If the main point of the language is to generate flops, flops should be an explicit primitive!

Well, firstly it isn't, as others have explained. It's broader - describe a digital logic circuit - efficiently.

Secondly, it's trivially possible to explicitly generate flip-flops and other hardware primitives using a more "structural" approach:

    DFF mydff(
      .clk (clk100),
      .rst, // means .rst(rst)
      .d   (in),
      .q   (out)
    );
Thirdly, the whole reason that we have "synthesis" is to allow a much higher-level description that is not so explicitly "structural". It gets really unwieldy otherwise:

    reg [127:0]out;
    always_ff @(posedge clk)
        out <= in;
There - I just made 128 of those flip-flops. Also, told you it was a "128 bit register that was clocked on the positive edge". One can at once describe the meaning of the circuit, describe the circuit, and make a event-driven-simulator of the circuit. For really large numbers of elements in a terse but understandable format.

It ain't perfect, but it's doing a lot more than I think a lot of people realize and a lot more than a lot of similar looking procedural languages do.

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